TiWi-SL MODULE
DATASHEET
SPI Timing
Figure 5 SPI Timing
Symbol
T clk
T p
Parameter
Clock period, CLK
High Pulse width (including jitter and duty cycle)
Min
62.5
25 (2)
Max
37.5
Unit
ns
ns
t is
T in
T os
T oh
C L
RX setup time; minimum time in which data is stable before edge capture
RX hold time; minimum time in which data is stable after edge capture
TX setup propagation time; maximum time from launch edge until data is stable
TX hold propagation time; minimum time of stable data after launch edge
Capacitive load on I/F
5
5
3
10.2
13
ns
ns
ns
ns
pF
Table 18 SPI Clock Switching Characteristics
(1)
(2)
SPI_CS is considered asynchronous.
40%-60% dc (valid for the minimum clock period)
The information in this document is subject to change without notice.
330-0085-R3.0
Copyright ? 2011-2012 LS Research, LLC
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